Method and system for testing oscillator circuit

ABSTRACT

An oscillator circuit generates a voltage signal. The magnitude of the voltage signal is measured and compared with predetermined upper and lower voltage signals by an internal test circuit. If the magnitude of the voltage signal is between the predetermined upper and lower voltage signals, then a pass test status signal is generated. If the magnitude of the voltage signal is not between the predetermined upper and lower voltage signals then a fail test status signal is generated.

BACKGROUND OF THE INVENTION

The present invention relates to electronic circuits, and morespecifically to a method and system for testing an oscillator circuit.

Oscillator circuits are an integral part of modern electronic circuits,especially microprocessor and microcontroller based circuits. Anoscillator circuit, such as a PLL (Phase Locked Loop) circuit and acrystal oscillator circuit, is used to generate a clock signal, which isused to synchronize operations between various elements of an electroniccircuit.

Crystal oscillator circuits are commonly used in the microprocessor andmicrocontroller based circuits for generating an oscillating signal. Themicroprocessor includes an on-chip circuit for generating a clock signalfrom the oscillating signal. Since, the circuit is on-chip, it may havesome silicon faults that can hamper its operation, thereby producing afaulty clock signal. It is therefore essential to test the on-chipcircuit to ensure generation of a correct clock signal.

Various testing techniques have been used to test the on-chip circuit.One test technique is to test the oscillation frequency with an externalcrystal having 100% fault coverage. In such case, the general start-uptime is around 500 ms-600 ms for a crystal oscillator with a 32 kHzcrystal. Thus, this technique has a long production test time. Thistechnique also cannot be used to test the silicon die before it has beenpackaged.

Another test technique requires using external voltage sources and anammeter to test the oscillator circuit. FIG. 1 is a schematic diagram ofan ammeter based system 100 for testing an oscillator circuit. Thesystem includes an on-chip inverter 102, which is connected between anEXTAL terminal 104 and an XTAL terminal 106. The system 100 alsoincludes a first voltage source 108 connected to the EXTAL terminal 104and a second voltage source 110 connected to an ammeter 112, whichin-turn is connected to the XTAL terminal 106.

FIG. 2 is a flowchart 200 illustrating a method for testing theoscillator circuit with the system 100. The method includes two tests,the first test of which is shown in FIG. 2.

At step 202, a first voltage signal is applied from the second voltagesource 110 at the XTAL terminal 106 and the EXTAL terminal 104 isgrounded. The inverter 102 draws a current signal, corresponding to thefirst voltage signal, from the second voltage source 110. At step 204,the current drawn from the voltage source 110 is measured using theammeter 112. At step 206, a check is performed to determine whether themagnitude of the measured current is within predefined limits. If themeasured current is within the predefined limit, then at step 208 a passstatus signal is generated; otherwise a fail status signal is generatedat step 210.

Subsequent to the first test, a second test is performed in which theXTAL terminal 106 is grounded and a second voltage signal from thesecond voltage source 108 is applied at the EXTAL terminal 104. Then themethod described above from steps 204 to 210 is repeated to detectsilicon faults. In other words, the magnitude of the voltage signalsgenerated by the first and second voltage sources 108, 110 are varied inorder to cover all the silicon faults present in the oscillator circuit.

This conventional testing technique requires a long setup time to insureadequate test accuracy. Thus, the production test time is long and thefault coverage is relatively low. Further, use of external voltagesources and an external ammeter increases cost. Accordingly, there isneed for a system for testing an oscillator circuit that has a lowproduction test time and high fault coverage.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description of the preferred embodiments of thepresent invention will be better understood when read in conjunctionwith the appended drawings. The present invention is illustrated by wayof example, and not limited by the accompanying figures, in which likereferences indicate similar elements.

FIG. 1 is a schematic diagram of a conventional system for testing anoscillator circuit;

FIG. 2 is a flow chart illustrating a conventional method for testing anoscillator circuit;

FIG. 3 is a flow chart illustrating a method for testing an oscillatorcircuit in accordance with an embodiment of the present invention;

FIG. 4 is a schematic diagram of a system for testing an inverter basedoscillator circuit in accordance with an embodiment of the presentinvention; and

FIG. 5 is a schematic diagram of a system for testing an ALC (AmplitudeLoop Control) based oscillator circuit in accordance with an embodimentof the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

The detailed description of the appended drawings is intended as adescription of the currently preferred embodiments of the presentinvention, and is not intended to represent the only form in which thepresent invention may be practiced. It is to be understood that the sameor equivalent functions may be accomplished by different embodimentsthat are intended to be encompassed within the spirit and scope of thepresent invention.

In an embodiment of the present invention a method for testing anoscillator circuit is provided in which the oscillator circuit is one ofan inverter based oscillator circuit or an ALC (Amplitude Loop Control)oscillator circuit. The oscillator circuit generates a voltage signal.The method includes, measuring the magnitude of the voltage signal andcomparing the magnitude of the voltage signal with a predetermined firstand second voltage signals by an internal test to generate a test statussignal that indicates either a pass or fail test status for theoscillator circuit.

In another embodiment of the present invention a system for testing anoscillator circuit is provided. The system includes an inverterconnected between an input terminal and an output terminal of theoscillator circuit. The inverter is configured to operate based on a DCbias point voltage. The system includes a first switch connected inparallel to the inverter and a second switch connected in series withthe first switch and to an internal test circuit. The internal testcircuit generates a test status signal by comparing the magnitude of theDC bias point voltage with predetermined first and second voltagelevels.

In yet another embodiment of the present invention a system for testingan oscillator circuit is provided. The oscillator circuit receives a DCsignal from an input terminal of the oscillator circuit. The systemincludes a bias circuit for generating a bias current signal and anamplitude detector that is connected to the bias circuit and to an inputterminal of the oscillator circuit. The amplitude detector generates abias voltage signal based on the DC signal received from the inputterminal of the oscillator. An amplifier receives the bias voltagesignal from the amplitude detector and generates an output voltagesignal based on the bias voltage signal. A plurality of switches isconnected to the amplifier to control the operation of the amplifierbased on a control signal. A resistance element is connected to theamplifier and the plurality of switches. The output voltage signal fromthe amplifier is generated across the resistive element. A comparatorcompares the output voltage signal with first and second voltage levelsto generate a test status signal.

Referring now to FIG. 3, a flow chart 300 illustrating a method fortesting an oscillator circuit in accordance with an embodiment of thepresent invention is shown. At 302, a voltage signal generated by theoscillator circuit is measured. In an embodiment of the presentinvention, the oscillator circuit is an inverter based oscillatorcircuit. In another embodiment of the present invention, the oscillatorcircuit is an ALC (Amplitude Loop Control) based oscillator circuit. Thegeneration of the voltage signal is explained later in conjunction withFIGS. 4 5. At 304 the voltage signal is compared with an upper limitvoltage signal. If, at 304, it is determined that the magnitude of thevoltage signal is greater than the upper limit voltage signal then, at310, a fail test status signal is generated. However, if at 304, it isdetermined that the magnitude of the voltage signal is less than theupper voltage limit then, at 306, the voltage signal is compared with alower limit voltage signal. If, at 306, it is determined that themagnitude of the voltage signal is less than the lower limit voltagesignal then step 310 is performed. At 310, a fail test status signal isgenerated. However, if at 306, it is determined that the magnitude ofthe voltage signal is greater than the lower limit voltage signal then,at 308, a pass test status signal is generated. In an embodiment of thepresent invention, the upper and lower limit voltages are set based onthe magnitude of the voltage signal generated by the oscillator circuit.For example, in one embodiment of the invention, the upper limit voltageis 120% of the magnitude of the voltage signal and the lower limitvoltage signal is 80% of the magnitude of the voltage signal.

FIG. 4 is a block diagram of a system 400 for testing an inverter basedoscillator circuit in accordance with an embodiment of the presentinvention. The system 400 includes an inverter 402, a first switch 404,a second switch 406, and an internal test circuit 408. The inverter 402is connected between an input terminal 410 and an output terminal 412.In an embodiment of the present invention, the inverter 402 is anamplifier, which is the device under test. The first switch 404 isconnected in parallel to the inverter 402 and the second switch 406 isconnected in series with the first switch 404 and the internal testcircuit 408. In an embodiment of the invention, the internal testcircuit 408 is an ADC (Analog to Digital Converter).

For testing the inverter based oscillator circuit, the first and secondswitches 404 and 406 are switched to an ON state. The internal testcircuit 408 is connected to the inverter 402 via the second switch 406.In one embodiment of the invention, the inverter 402 includes a PMOStransistor and an NMOS transistor, which operate at a DC bias pointvoltage when the first switch 404 is switched to the ON state. Themagnitude of the DC bias point voltage is determined by the size ratioof the PMOS and NMOS transistors. For instance, if the size ratio of thePMOS and NMOS transistors is the same, the DC bias voltage for both theNMOS and PMOS transistors is the same. In an embodiment of the presentinvention, the system 400 is used for testing an oscillator circuit thatincludes a plurality of inverters that further include a plurality ofNMOS transistors and a plurality of PMOS transistors having the samesize ratio. Due to this same size ratio, the DC bias point voltages ofthe plurality of inverters are the same.

Switching the first switch 404 to the ON state leads to the generationof the DC bias point voltage across the input terminal 410 and theoutput terminal 412. Since the second switch 406 is in the ON state, theDC bias point voltage is detected by the internal test circuit 408. Theinternal test circuit 408 compares the magnitude of the DC bias pointvoltage with a predetermined upper limit voltage level and apredetermined lower limit voltage level. If the magnitude of the DC biaspoint voltage lies between the predetermined upper and lower limitvoltage levels, a pass test status signal is generated. The pass teststatus signal indicates that the inverter based oscillator circuit isnot faulty. However, if the magnitude of the DC bias point voltage doesnot lie between the predetermined upper and lower limit voltage levels,a fail test status signal is generated. The fail test status signalindicates that the inverter based oscillator circuit is faulty. In anembodiment of the present invention the upper limit voltage level andthe lower limit voltage level are determined based on the DC biasvoltage of the inverter 402.

In another embodiment of the present invention, the system 400 is usedfor testing an oscillator circuit that includes a single inverter usinga dummy inverter with the same size ratio as that of the singleinverter.

FIG. 5 is a diagram of a system 500 for testing an ALC based oscillatorcircuit in accordance with an embodiment of the present invention. Thesystem 500 includes a bias circuit 502, a first amplifier 504, a peakdetector 506, a PMOS transistor 508, an NMOS transistor 510, aresistance element 512, a first switch 514 a, a second switch 514 b, athird switch 524, a fourth switch 526, and an internal test circuit 528.The system 500 receives a first control signal 520 and a second controlsignal 522 for controlling the switching of the first, second, third andfourth switches 514 a, 514 b, 524, and 526. The bias circuit 502includes a current mirror circuit (not shown) and a resistor (not shown)connected to the current mirror circuit.

The bias circuit 502 is connected to the first amplifier 504. Thepositive input terminal of the first amplifier 504 is connected to thepeak detector 506 and the negative terminal of the first amplifier 504receives a reference voltage signal generated by an on-chip circuit (notshown). The output terminal of the first amplifier 504 is connected tothe gate terminal of the PMOS transistor 508. In an embodiment of thepresent invention the first amplifier 504 and the peak detector 506together form an amplitude detector circuit 516. The source terminal ofthe PMOS transistor 508 is connected to a voltage source (VDD) and thedrain terminal of the PMOS transistor 508 is connected to the drainterminal of the NMOS transistor 510. The drain terminal of the PMOStransistor 508 also is connected to the resistance element 512. Thesource terminal of the NMOS transistor 510 is grounded. In an embodimentof the present invention the NMOS transistor 510 and the PMOS transistor508 connected as described above form a second amplifier 518, which isthe amplifier of the ALC based oscillator under test. In an embodimentof the invention, the amplifier 518 is a MOSFET based amplifier. Thegate terminal of the NMOS transistor 510 is connected to the peakdetector 506 through the third switch 524. The gate terminal of the NMOStransistor 510 also is connected to the first switch 514 a. The peakdetector 506 is connected to the input terminal 410.

The system 500 receives the first and second control signals 520 and522. The first control signal 520 controls the switching of the firstswitch 514 a, second switch 514 b and third switch 524. On receiving thefirst control signal 520, the first and second switches 514 a and 514 bswitch to an ON state while the third switch 524 switches to an OFFstate. Since the first switch 514 a is ON, the gate terminal of the NMOStransistor 510 is grounded. The peak detector 506 receives a DC signalfrom the input terminal 410. On receiving the DC signal, the peakdetector 506 generates a voltage signal having a magnitude equal to themagnitude of the reference voltage signal. The output voltage signal istransmitted to the positive terminal of the first amplifier 504. Thefirst amplifier 504 also receives a bias current signal from the biascircuit 502. In an embodiment of the present invention, the bias currentsignal is inversely proportional to the resistor in the bias circuit502. In another embodiment of the present invention, the first amplifier504 operates based on a tail current of the first amplifier 504, whichis a multiple of the bias current signal received from the bias circuit502. The first amplifier 504 generates a bias voltage signal based onthe voltage signal from the peak detector 506 and the reference voltagesignal. The bias voltage signal is applied at the gate terminal of thePMOS 508. Since the gate terminal of the NMOS transistor 510 isgrounded, the NMOS transistor 510 is operating in the cut-off region.Thus, the PMOS transistor 508 generates an output current signal basedon the bias voltage signal. In an embodiment of the present invention,the output current signal is a multiple of the tail current when themagnitude of the reference voltage is the same as the magnitude of theDC voltage. It should be understood by those of skill in the art thatthe output current is M times the bias current signal from the biascircuit 502, where ‘M’ is the multiplication factor between the biascircuit 502 and the PMOS transistor 508. It also should be known bythose of skill in the art that since the bias current signal isinversely proportional to the resistor in the bias circuit 502, theoutput current signal flowing through the PMOS transistor 508 is alsoinversely proportional to the resistor in the bias circuit 502. Theoutput current flows through the resistance element 512 to generate anoutput voltage signal. In a preferred embodiment, the type of theresistance element 512 is the same as the resistor of the bias circuit502, and the magnitude of the resistance element 512 is proportional tothe magnitude of the resistor in the bias circuit 502. For this reason,the output voltage signal formed across the resistance element 512 is alinear function of the bias current signal from the bias circuit 502 andcorresponds to the whole circuit from bias circuit 502 to the PMOStransistor 508.

The output voltage signal is transmitted to the internal test circuit528. The internal test circuit 528 compares the magnitude of the outputvoltage signal with a predetermined upper limit voltage level and apredetermined lower limit voltage level. If it is determined that themagnitude of the output voltage signal lies between the predeterminedupper and lower limit voltage levels, a pass test status signal isgenerated. The pass test status signal indicates that the ALC basedoscillator circuit is not faulty. However, if it is determined that themagnitude of the DC bias point voltage does not lie between thepredetermined upper and lower limit voltage levels, a fail test statussignal is generated. The fail test status signal indicates that the ALCbased oscillator circuit is faulty. In an embodiment of the presentinvention the upper and lower limit voltages are set based on themagnitude of the voltage signal generated by the oscillator circuit. Forexample, in one embodiment of the invention, the upper limit voltage is120% of the magnitude of the voltage signal and the lower limit voltagesignal is 80% of the magnitude of the voltage signal. In anotherembodiment of the present invention, the output voltage signal formedacross the resistance element 512 is a linear function of the output ofbias circuit 502, amplitude detector 516, and the PMOS transistor 508.Thus the output voltage corresponds to the complete circuit and anydiscrepancy in the circuit is reflected in the output voltage signal.

The method and the system described above have numerous advantages. Thesystem has higher production test coverage and a shorter production testtime with only a very small layout size increase. The system describedabove does not require external voltage sources and an ammeter to testthe oscillator circuit. Instead of the external voltage sources andexternal ammeter, the system uses a voltage signal, generatedinternally, to test the oscillator circuit. Thus, the test time isreduced. Further, the above described system and method for testing theoscillator circuit is more efficient in comparison to the conventionalmethods and system. And as the method does not need to conductfrequency/time measurement, the method is suitable for lower costtesters.

While various embodiments of the present invention have been illustratedand described, it will be clear that the present invention is notlimited to these embodiments only. Numerous modifications, changes,variations, substitutions, and equivalents will be apparent to thoseskilled in the art, without departing from the spirit and scope of thepresent invention, as described in the claims.

1. (canceled)
 2. A system for testing an oscillator circuit, comprising:an inverter connected between an input terminal and an output terminalof the oscillator circuit, the inverter being configured to operatebased on a DC bias point voltage; a first switch connected in parallelto the inverter; a second switch connected in series with the firstswitch; and an internal test circuit that generates a test status signalby comparing a magnitude of the DC bias point voltage with first andsecond voltage levels, wherein the internal test circuit measures themagnitude of the DC bias point voltage based on a state of the firstswitch and a state of the second switch.
 3. The system of the claim 2,wherein both the first switch and the second switch are switched to atleast one of an ON state and an OFF state at same time.
 4. The system ofthe claim 2, wherein the internal test circuit measures the magnitude ofthe DC bias point state voltage when the first switch and the secondswitch are in an ON state.
 5. The system of the claim 2, wherein theinternal test circuit includes a comparator for comparing the DC biaspoint voltage with the first and second voltage levels to generate thetest status signal, wherein the test status signal signifies at leastone of a pass status and a fail status of the oscillator circuit.
 6. Thesystem of claim 5, wherein the internal test circuit is an ADC (Analogto Digital Converter).
 7. The system of claim 2, wherein the inverter isan amplifier.
 8. The system of claim 7, wherein the amplifier is a classA amplifier. 9-16. (canceled)